Pci Express Base Specification Revision 6.0 -

Publication Date: January 11, 2022 (PCI-SIG) Report Author: Technical Analysis Unit Document Type: Specification Overview & Impact Analysis 1. Executive Summary PCI Express (PCIe) 6.0 represents a paradigm shift in high-speed interconnect technology, doubling the data rate of PCIe 5.0 from 32 GT/s to 64 GT/s while maintaining backward compatibility with all previous generations. For the first time in the technology’s history, PCIe 6.0 transitions from Non-Return to Zero (NRZ) signaling to Pulse Amplitude Modulation with 4 levels (PAM-4) and introduces Low-Latency Forward Error Correction (FEC) with Flow Control Unit (FLIT) encoding . This report details the technical specifications, architectural changes, and ecosystem implications of PCIe 6.0. 2. Key Performance Metrics | Parameter | PCIe 5.0 | PCIe 6.0 | Improvement | | :--- | :--- | :--- | :--- | | Data Rate | 32 GT/s | 64 GT/s | 2x | | x16 Bandwidth (bidirectional) | ~128 GB/s | ~256 GB/s | 2x | | x16 Bandwidth (unidirectional) | ~64 GB/s | ~128 GB/s | 2x | | Encoding Scheme | 128b/130b NRZ | PAM-4 + FLIT | New | | FEC | Optional (Replay) | Mandatory (Lightweight) | New | | Target Markets | Cloud, Enterprise AI | AI/ML, HPC, 800G Ethernet | Expanded | 3. Fundamental Architectural Changes 3.1 Transition from NRZ to PAM-4 Signaling Prior generations (1.0 through 5.0) used Non-Return to Zero (NRZ) signaling, where two voltage levels represented bits 0 and 1. PCIe 6.0 adopts Pulse Amplitude Modulation with 4 levels (PAM-4) . In PAM-4, each symbol period carries 2 bits (four voltage levels: -1, -1/3, +1/3, +1).